Engineering samples of AMD's next-generation EPYC datacenter CPUs, codenamed Venice, have emerged online, revealing impressive core density specifications ahead of the Zen 6 architecture's anticipated 2027 launch. Discovered on OpenBenchmark.org by user Olrak29_, the leaked test results provide a rare glimpse into the silicon for the upcoming SP7 socket platform, which promises to significantly outperform the current Turin generation in memory bandwidth and core capacity. The published data includes results from six different test configurations. Samples identified by part numbers such as 100-000001056-09 were tested on the Kenya platform, featuring a 128-core configuration with four Core Complex Dies (CCDs) and two I/O Dies (IODs). Other samples were evaluated on the Nigeria platform, where setups utilized dual CPUs. Notably, a high-end sample, 100-000001051-08, demonstrated a massive 192-core configuration powered by eight CCDs and two IODs. Mid-range samples also appeared, including a 64-core model with two CCDs and a 128-core model with four CCDs. Analysis of these samples indicates that the Venice chips likely utilize a new, space-optimized variant of the Zen 6 architecture, designated as Zen 6c. The data shows a clear shift toward higher-density CCDs compared to the previous Zen 5 generation. While the 64-core and 128-core models utilize 32 cores per CCD, the top-tier 192-core variant employs 24 cores per CCD. This aligns with prior rumors suggesting that the standard Zen 6 cores will be housed in 12-core CCDs, while the density-optimized Zen 6c cores will pack up to 32 cores per module. Additionally, reports suggest AMD is increasing the L3 cache capacity to 48MB for the architecture. Regarding clock speeds, one of the available 64-core samples peaked at 3.54GHz during stress tests, though performance data for other samples remains limited as some listings have been removed. Zen 6 is slated to reach the datacenter market in 2027, with flagship parts expected to support up to 256 cores. While AMD traditionally launches consumer architecture before enterprise solutions, the timeline suggests a potential reversal. The company has confirmed a 2026 release window for the Venice EPYC series but has not provided a specific launch date for the consumer edition, codenamed Olympic Ridge. This strategic shift may indicate AMD's intent to capitalize on renewed demand in the datacenter sector by prioritizing its enterprise silicon. No official details have been released regarding the consumer Olympic Ridge platform, leaving the release order and specifications for retail processors uncertain.